Project Support


Contexts:Network socket, serial console.
Function:Resets the STARGRASP FPGA board into its power-on state, "stage1".
Required Parameters:none.
Optional Parameters:keeplog - Causes reset to keep the log of recent message intact just like an unexpected reset, so they will all get displayed when stage1 reboots.

This command does not reset any analog functions. Specifically, DAC outputs get left where they were and only the CPU in the FPGA is reset. Use "dac init" before "reset" to bring all DAC outputs back to 50 mV.


If the "dac init" Vref value is left at a non-standard offset, the DACs may be inoperable after a soft reset.

If "stage1" code in BRAM has been corrupted, power cycling may be required.